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| THURSDAY, June 10, 2004, 10:30 AM - 12:00 PM | Room: 4 | ||
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TOPIC AREA: LOGIC DESIGN AND TEST | ||
| SESSION 45 | |||
| FPGA-Based Systems | |||
| Chair: Katherine Compton - Univ. of Wisconsin, Madison, WI | |||
| Organizers: Jens Palsberg, Scott Hauck | |||
| The heterogeneity of newer FPGAs is driving new classes of systems, and corresponding problems, for the FPGA CAD designer. With multiple resources, traditional algorithms such as partitioning must be reformulated to deal with these constraints. Power and power minimization is also crucial, forcing changes in architecture and algorithms. These new architectures give rise to new uses, such as mixed-mode simulators. | |||
 45.1 |
FPGA Power Reduction Using Configurable Dual-Vdd |
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| Speaker(s): | Fei Li - Univ. of California, Los Angeles, CA | ||
| Author(s): | Fei Li - Univ. of California, Los Angeles, CA Yan Lin - Univ. of California, Los Angeles, CA Lei He - Univ. of California, Los Angeles, CA Jason Cong - Magma Design Automation, Inc., Los Angeles, CA | ||
| 45.2 | Multi-Resource Aware Partitioning Algorithms for FPGAs with Heterogeneous Resources | ||
| Speaker(s): | Navaratnasothie Selvakkumaran - Univ. of Minnesota, Minneapolis, MN | ||
| Author(s): | Navaratnasothie Selvakkumaran - Univ. of Minnesota, Minneapolis, MN Abishek Ranjan - Hier Design Inc., Santa Clara, CA Salil Raje - Hier Design Inc., Santa Clara, CA George Karypis - Univ. of Minnesota, Minneapolis, MN | ||
| 45.3 | An SoC Design Methodology Using FPGA and Embedded Microprocessors | ||
| Speaker(s): | Nobuyuki Ohba - IBM Corp., Sendai, Japan | ||
| Author(s): | Nobuyuki Ohba - IBM Corp., Sendai, Japan Kohji Takano - IBM Corp., Yamato, Japan | ||
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